SM320F28335PTPMEP Datasheet, PDF (135/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
(A)(B)
Lead
Active
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
(D)
XWE0, XWE1
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_{d(XCOHL-XZCSH)}
t_{d(XCOHL-XRDH)}
t_su(XD)XRD
XR/W
XD[0:31], XD[0:15]
(E)
XREADY
t_a(A)
t_a(XRD)
t_h(XD)XRD
DIN
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-24. Example Read Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
≥1
≥0
≥0
0
0
(1) N/A = Not applicable (or “Don’t care”) for this example
XWRLEAD
N/A ⁽¹⁾
XWRACTIVE
N/A ⁽¹⁾
XWRTRAIL
N/A ⁽¹⁾
READYMODE
N/A ⁽¹⁾
6.14.6 External Interface Write Timing
Table 6-39. External Interface Write Switching Characteristics
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XWEL)}
t_{d(XCOHL-XWEH)}
t_{d(XCOH-XRNWL)}
t_{d(XCOHL-XRNWH)}
t_en(XD)XWEL
t_d(XWEL-XD)
t_h(XA)XZCSH
PARAMETER
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 ⁽¹⁾ low
Delay time, XCLKOUT high/low to XWE0, XWE1 high
Delay time, XCLKOUT high to XR/W low
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
MIN
MAX UNIT
1 ns
–1
0.5 ns
1.5 ns
2 ns
2 ns
1 ns
-1
0.5 ns
0
ns
1 ns
(2)
ns
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.
(2) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
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Electrical Specifications 135