SM320F28335PTPMEP Datasheet, PDF (144/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
XCLKOUT
(/1 Mode)
XHOLD
XHOLDA
XR/W
XZCS0, XZCS6, XZCS7
t_d(HL-Hiz)
t_d(HL-HAL)
t_d(HH-HAH)
t_d(HH-BV)
High-Impedance
XA[19:0]
Valid
High-Impedance
Valid
XD[31:0], XD[15:0]
Valid
(A)
(B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-30. External Interface Hold Waveform
Table 6-48. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)^{(1) (2) (3)}
MIN
MAX
UNIT
t_d(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all address, data, and
control
4t_{c(XTIM) + tc(XCO) + 30 ns}
ns
t_d(HL-HAL)
t_d(HH-HAH)
t_d(HH-BV)
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
4t_{c(XTIM + 2tc(XCO) + 30 ns}
ns
4t_{c(XTIM) + 30 ns}
ns
6t_{c(XTIM) + 30 ns}
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
144 Electrical Specifications
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