SM320F28335PTPMEP Datasheet, PDF (73/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
NOTE
The temperature rating of any recommended component must match the rating of the end
product.
4.7.1 ADC Connections if the ADC Is Not Used
It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
• V_DD1A18/V_DD2A18 – Connect to V_DD
• V_DDA2, V_DDAIO – Connect to V_DDIO
• V_SS1AGND/V_SS2AGND, V_SSA2, V_SSAIO – Connect to V_SS
• ADCLO – Connect to V_SS
• ADCREFIN – Connect to V_SS
• ADCREFP/ADCREFM – Connect a 100-nF cap to V_SS
• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to V_SS.
• ADCINAn, ADCINBn - Connect to V_SS
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (V_SS1AGND/V_SS2AGND)
NOTE
ADC parameters for gain error and offset error are specified only if the ADC calibration
routine is executed from the Boot ROM. See Section 4.7.3 for more information.
4.7.2 ADC Registers
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6.
Table 4-6. ADC Registers⁽¹⁾
NAME
ADCTRL1
ADCTRL2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADDRESS ⁽¹⁾
0x7100
0x7101
0x7102
0x7103
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
ADDRESS ⁽²⁾
0x0B00
0x0B01
0x0B02
0x0B03
0x0B04
SIZE (x16)
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
ADC Control Register 1
ADC Control Register 2
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
(1) The registers in this column are Peripheral Frame 2 Registers.
(2) The ADC result registers are dual mapped. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left justified.
Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 1 wait-state for CPU accesses and 0 wait state for DMA accesses and right
justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user
memory.
Copyright © 2009–2012, Texas Instruments Incorporated
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