SM320F28335PTPMEP Datasheet, PDF (75/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
4.8 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
• Full–duplex communication
• Double–buffered data registers that allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• A wide selection of data sizes including 8–, 12–, 16–, 20–, 24–, or 32–bits
• 8–bit data transfers with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Direct interface to industry–standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
• Works with SPI–compatible devices
• The following application interfaces can be supported on the McBSP:
– T1/E1 framers
– IOM–2 compliant devices
– AC97–compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS–compliant devices
– SPI
• McBSP clock rate,
CLKSRG
CLKG =
(1+ CLKGDV)
(1)
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit.
NOTE
See Section 6 for maximum I/O pin toggling speed.
Figure 4-11 shows the block diagram of the McBSP module.
Copyright © 2009–2012, Texas Instruments Incorporated
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