SM320F28335PTPMEP Datasheet, PDF (114/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
6.9.2 GPIO - Input Timing
GPIO Signal
(A)
GPxQSELn = 1,0 (6 samples)
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1100000001000111111111
SYSCLKOUT
t_w(IQSW)
Sampling Window
t_w(SP)
Sampling Period determined
by GPxCTRL[QUALPRD]^(B)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5^(C))
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-11. Sampling Mode
Table 6-12. General-Purpose Input Timing Requirements
MIN MAX
t_w(SP)
t_w(IQSW)
t_w(GPI) ⁽²⁾
Sampling period
Input qualifier sampling window
Pulse duration, GPIO low/high
QUALPRD = 0
QUALPRD ≠ 0
Synchronous mode
With input qualifier
1t_c(SCO)
2t_c(SCO) * QUALPRD
t_w(SP) * (n ⁽¹⁾ – 1)
2t_c(SCO)
t_w(IQSW) + t_w(SP) + 1t_c(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For t_w(GPI), pulse width is measured from V_IL to V_IL for an active low signal and V_IH to V_IH for an active high signal.
UNIT
cycles
cycles
cycles
cycles
cycles
114 Electrical Specifications
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