SM320F28335PTPMEP Datasheet, PDF (153/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
NO.
M7
t_d(CKXH-DXV)
M8
t_en(CKXH-DX)
M9
t_d(FXH-DXV)
M10 t_en(FXH-DX)
CLKR
FSR (int)
FSR (ext)
DR
(RDATDLY=00b)
DR
(RDATDLY=01b)
DR
(RDATDLY=10b)
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 6-55. McBSP Switching Characteristics^{(1) (2)} (continued)
PARAMETER
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
Delay time, CLKX high to DX valid
DXENA = 0
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
Enable time, CLKX high to DX driven DXENA = 0
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
Delay time, FSX high to DX valid
DXENA = 0
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode.
Enable time, FSX high to DX driven
DXENA = 0
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
MIN
0
6
P
P+6
0
6
P
P+6
MAX
9
28
8
14
P+8
P + 14
UNIT
ns
ns
8 ns
14
P+8
P + 14
ns
M1, M11
M2, M12
M13
M3, M12
M4
M4
M15
M16
M18
M17
Bit (n−1)
M17
(n−2)
Bit (n−1)
M17
(n−3)
M18
(n−2)
Bit (n−1)
Figure 6-36. McBSP Receive Timing
M14
(n−4)
(n−3)
M18
(n−2)
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-EP
Electrical Specifications 153