C8051F321-GMR Datasheet, PDF (90/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
Table 9.4. Interrupt Summary (Continued)
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flag
Enable
Flag
Priority
Control
ADC0 Conversion
Complete
Programmable
Counter Array
Comparator0
Comparator1
Timer 3 Overflow
VBUS Level
0x0053
0x005B
0x0063
0x006B
0x0073
0x007B
10
AD0INT (ADC0CN.5) Y
N
EADC0
(EIE1.3)
PADC0
(EIP1.3)
11
CF (PCA0CN.7)
CCFn (PCA0CN.n)
Y
N
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
12
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
N
N
ECP0
(EIE1.5)
PCP0
(EIP1.5)
13
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
N
N
ECP1
(EIE1.6)
PCP1
(EIP1.6)
14
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N
N
ET3
(EIE1.7)
PT3
(EIP1.7)
15 N/A
N/A
N/A
EVBUS
(EIE2.0)
PVBUS
(EIP2.0)
9.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
90
Rev. 1.4