C8051F321-GMR Datasheet, PDF (67/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
8. Voltage Regulator (REG0)
C8051F320/1 devices include a 5-to-3 V voltage regulator (REG0). When enabled, the REG0 output
appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by
software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics.
Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered
function. REG0 configuration options are shown in Figure 8.2–Figure 8.5.
The input (VREGIN) and output (VDD) of the voltage regulator should both be protected by adding decou-
pling and bypass capacitors on each pin to ground. Suggested values for the two capacitors are
4.7 µF + 0.1 µF. These capacitors will increase noise immunity and stabilize the voltage supply.
REG0
4.7 µF
V_DD
4.7 µF
V_REGIN
0.1 µF
V_DD
0.1 µF
Figure 8.1. External Capacitors for Voltage Regulator Input/Output
8.1. Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is
degraded. See Table 8.1 for normal and low power mode supply current specifications. The REG0 mode
selection is controlled via the REGMOD bit in register REG0CN.
8.2. VBUS Detection
When the USB Function Controller is used (see section Section “15. Universal Serial Bus Controller
(USB)” on page 139), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register
REG0CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be gener-
ated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The
VBUS interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be
active as long as the VBUS signal matches the polarity selected by VBPOL. See Table 8.1 for VBUS input
parameters.
Rev. 1.4
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