C8051F321-GMR Datasheet, PDF (58/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and supply current falls to less than 100 nA. See Section “14.1. Priority Crossbar Decoder” on page 128
for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally
driven from –0.25 V to (V_DD) + 0.25 V without damage or upset. The complete Comparator electrical spec-
ifications are given in Table 7.1.
Comparator response time may be configured in software via the CPTnMD registers (see Figure 7.3 and
Figure 7.6). Selecting a longer response time reduces the Comparator supply current. See Table 7.1 for
complete timing and supply current specifications.
CMX1N1
CMX1N0
CMX1P1
CMX1P0
P1.2
P1.6
P2.2
P2.6
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1 +
P1.3
P1.7
P2.3
P2.7
CP1 -
VDD
CP1
Interrupt
+
-
GND
CP1
Rising-edge
CP1
Falling-edge
D ^SET Q
Q
CLR
D ^SET Q
Q
CLR
(SYNCHRONIZER)
Interrupt
Logic
CP1RIE
CP1FIE
CP1
Crossbar
CP1A
Note: P2.6 and P2.7 available
only on C8051F320
CP1RIE
CP1FIE
CP1MD1
CP1MD0
Figure 7.2. Comparator1 Functional Block Diagram
58
Rev. 1.4