C8051F321-GMR Datasheet, PDF (137/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
SFR Definition 14.15. P3: Port3 Register
R/W
P3.7
Bit7
R/W
P3.6
Bit6
R/W
P3.5
Bit5
R/W
P3.4
Bit4
R/W
P3.3
Bit3
R/W
P3.2
Bit2
R/W
R/W
Reset Value
P3.1
P3.0 11111111
Bit1
Bit0 SFR Address:
(bit addressable) 0xB0
Bits7–0:
P3.[7:0]
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port
pin when configured as digital input.
0: P3.n pin is logic low.
1: P3.n pin is logic high.
SFR Definition 14.16. P3MDIN: Port3 Input Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
-
-
-
00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xF4
Bits7–1:
Bit0:
UNUSED. Read = 0000000b; Write = don’t care.
Analog Input Configuration Bit for P3.0.
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P3.n pin is configured as an analog input.
1: Corresponding P3.n pin is not configured as an analog input.
SFR Definition 14.17. P3MDOUT: Port3 Output Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
-
-
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA7
Bits7–1:
Bit0:
UNUSED. Read = 0000000b; Write = don’t care.
Output Configuration Bit for P3.0; ignored if corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
Rev. 1.4
137