C8051F321-GMR Datasheet, PDF (230/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
(for n = 0 to 4)
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n n n F
6nnn
n
n
PCA Counter/
Timer Overflow
PCA0CN
CC CCCCC
FR CCCCC
FFFFF
43210
PCA0MD
C WW
I DD
DTL
L EC
K
CCCE
PPPC
SSSF
210
0
1
PCA Module 0
(CCF0)
PCA Module 1
(CCF1)
PCA Module 2
(CCF2)
PCA Module 3
(CCF3)
PCA Module 4
(CCF4)
ECCF0
0
1
ECCF1
0
1
EPCA0
EA
0
1
ECCF2
0
1
ECCF3
0
1
ECCF4
0
1
Figure 20.3. PCA Interrupt Block Diagram
0 Interrupt
Priority
1
Decoder
20.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
230
Rev. 1.4