C8051F321-GMR Datasheet, PDF (83/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
Description
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
TMR3CN
0x91
Timer/Counter 3Control
TMR3H
0x95
Timer/Counter 3 High
TMR3L
0x94
Timer/Counter 3Low
TMR3RLH
0x93
Timer/Counter 3 Reload High
TMR3RLL
0x92
Timer/Counter 3 Reload Low
USB0ADR
0x96
USB0 Indirect Address Register
USB0DAT
0x97
USB0 Data Register
USB0XCN
0xD7
USB0 Transceiver Control
VDM0CN
0xFF
VDD Monitor Control
XBR0
0xE1
Port I/O Crossbar Control 0
XBR1
0xE2
Port I/O Crossbar Control 1
0x84–0x86, 0xAB-0xAF,
0xB4, 0xB5, 0xBF, 0xC7,
0xCE, 0xCF, 0xD2, 0xD3,
0xDF, 0xE3, 0xE5, 0xF5
Reserved
Page
221
225
226
226
226
226
143
144
141
101
131
132
9.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
SFR Definition 9.1. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
Rev. 1.4
83