C8051F321-GMR Datasheet, PDF (100/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
10.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above
V_RST. A Power-On Reset delay (T_PORDelay) occurs before the device is released from reset; this delay is
typically less than 0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.
VDD
2.70
2.4
V_RST
2.0
1.0
t
/RST
Logic HIGH
Logic LOW
T_PORDelay
Power-On
Reset
VDD
Monitor
Reset
Figure 10.2. Power-On and VDD Monitor Reset Timing
100
Rev. 1.4