C8051F321-GMR Datasheet, PDF (24/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4 / WDT
Crossbar
Port I/O
Figure 1.9. PCA Block Diagram
1.9. 10-Bit Analog to Digital Converter
The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multi-
plexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB.
The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC
inputs. Ports1-3 are available as ADC inputs; additionally, the on-chip Temperature Sensor output and the
power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the ADC to save
power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
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Rev. 1.4