C8051F321-GMR Datasheet, PDF (167/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
USB Register Definition 15.22. EOUTCSRH: USB0 OUT Endpoint Control Low Byte
R/W
R/W
R/W
R/W
R
R
R
R
DBOEN ISO
-
-
-
-
-
-
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7:
Bit6:
Bits5–0:
DBOEN: Double-buffer Enable
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
ISO: Isochronous Transfer Enable
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
Unused. Read = 000000b; Write = don’t care.
Reset Value
00000000
USB Address:
0x15
USB Register Definition 15.23. EOUTCNTL: USB0 OUT Endpoint Count Low
R
R
R
R
R
R
R
R
Reset Value
EOCL
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 USB Address:
0x16
Bits7–0: EOCL: OUT Endpoint Count Low Byte
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
USB Register Definition 15.24. EOUTCNTH: USB0 OUT Endpoint Count High
R
R
R
R
R
R
R
R
Reset Value
-
-
-
-
-
-
E0CH
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 USB Address:
0x17
Bits7–2:
Bits1–0:
Unused. Read = 000000b. Write = don’t care.
EOCH: OUT Endpoint Count High Byte
EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
Rev. 1.4
167