C8051F321-GMR Datasheet, PDF (118/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
Important Note: If the sum of the reset value of OSCICL and OSCICL is greater than 31 or less than 0,
then the device will not be capable of producing the desired frequency.
13.1.2. Internal Oscillator Suspend Mode
The internal oscillator may be placed in Suspend mode by writing ‘1’ to the SUSPEND bit in register
OSCICN. In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected (Sec-
tion 15) or VBUS matches the polarity selected by the VBPOL bit in register REG0CN (Section 8.2). The
transceiver is able to detect non-idle USB events even when it is placed in Suspend mode. On a non-idle
USB event, a Resume interrupt is generated, on receipt of which the PHYEN bit should be set to '1' to re-
enable the transceiver.
SFR Definition 13.1. OSCICN: Internal Oscillator Control
R/W
R
R/W
R
R/W
R/W
R/W
R/W
Reset Value
IOSCEN IFRDY SUSPEND -
-
-
IFCN1 IFCN0 10000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB2
Bit7:
Bit6:
Bit5:
Bits4–2:
Bits1–0:
IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
SUSPEND: Force Suspend
Writing a ‘1’ to this bit will force the internal oscillator to be stopped. The oscillator will be re-
started on the next non-idle USB event (i.e., RESUME signaling) or VBUS interrupt event
(see Figure 8.1).
UNUSED. Read = 000b, Write = don't care.
IFCN1–0: Internal Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.
SFR Definition 13.2. OSCICL: Internal Oscillator Calibration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
OSCCAL
Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB3
Bits7–5: Unused: Read = varies. Write = don’t care.
Bits4–0: OSCCAL: Oscillator Calibration Value
These bits determine the internal oscillator period as per Equation 13.1.
Note: The contents of this register are undefined when Clock Recovery is enabled. See Section “15.4. USB Clock
Configuration” on page 146 for details on Clock Recovery.
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Rev. 1.4