C8051F321-GMR Datasheet, PDF (152/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low
R
R
R
R
R
R
R
Frame Number Low
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bits7-0: Frame Number Low
This register contains bits7-0 of the last received frame number.
R
Reset Value
00000000
Bit0 USB Address:
0x0C
USB Register Definition 15.10. FRAMEH: USB0 Frame Number High
R
R
R
R
R
R
R
R
-
-
-
-
-
Frame Number High
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7-3: Unused. Read = 0. Write = don’t care.
Bits2-0: Frame Number High Byte
This register contains bits10-8 of the last received frame number.
Reset Value
00000000
USB Address:
0x0D
15.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in Figure 15.11 through
Figure 15.13. The associated interrupt enable bits are located in the USB registers shown in Figure 15.14
through Figure 15.16. A USB0 interrupt is generated when any of the USB interrupt flags is set to ‘1’. The
USB0 interrupt is enabled via the EIE1 SFR (see Section “9.3. Interrupt Handler” on page 87).
Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’.
152
Rev. 1.4