C8051F321-GMR Datasheet, PDF (237/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
20.3.1. Watchdog Timer Operation
While the WDT is enabled:
• PCA counter is forced on.
• Writes to PCA0L and PCA0H are not allowed.
• PCA clock source bits (CPS2-CPS0) are frozen.
• PCA Idle control bit (CIDL) is frozen.
• Module 4 is forced into Watchdog Timer mode.
• Writes to the Module 4 mode register (PCA0CPM4) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is loaded
into PCA0CPH4 (See Figure 20.10).
PCA0MD
CWW
I DD
DT L
LEC
K
CCCE
PPPC
SSSF
210
PCA0CPH4
8-bit
Enable ^Comparator
Match
Reset
PCA0CPL4
8-bit Adder
PCA0H
PCA0L Overflow
Write to
PCA0CPH4
Adder
Enable
Figure 20.10. PCA Module 4 with Watchdog Timer Enabled
Rev. 1.4
237