C8051F321-GMR Datasheet, PDF (77/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
9.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 9.2.
PROGRAM/DATA MEMORY
(Flash)
0x3E00
0x3DFF
RESERVED
0xFF
0x80
0x7F
16 K Flash
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Same 2048 bytes as from
0x0000 to 0x07FF, wrapped
on 2 kB boundaries
0x0800
0x07FF
0x0400
0x03FF
0x0000
USB FIFOs
1024 Bytes
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
Figure 9.2. Memory Map
9.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F320/1 implements 16k bytes of this
program memory space as in-system, re-programmable Flash memory, organized in a contiguous block
from addresses 0x0000 to 0x3FFF. Addresses above 0x3DFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to Section “11. Flash Memory” on page 106 for further details.
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