C8051F321-GMR Datasheet, PDF (19/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
VDD
Px.x
Px.x
Comparator 0
+
-
C0RSEF
Supply
Monitor
+
-
Enable
Power On
Reset
'0'
(wired-OR)
/RST
Internal
Oscillator
Missing
Clock
Detector
(one-
shot)
EN
PCA
WDT
EN
Software Reset (SWRSF)
Errant
FLASH
Operation
Reset
Funnel
XTAL1
XTAL2
Clock
Multiplier
External
Oscillator
Drive
System
Clock
Clock Select
CIP-51
Microcontroller ^{System Reset}
Core
USB
Controller
Extended Interrupt
Handler
Figure 1.3. On-Chip Clock and Reset
VBUS
Transition
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 16 kB of Flash. This memory may be reprogrammed in-system in 512 byte
sectors, and requires no special off-chip programming voltage. See Figure 1.4 for the MCU system mem-
ory map.
Rev. 1.4
19