C8051F321-GMR Datasheet, PDF (148/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
15.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for
Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN
Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for
the entire endpoint FIFO. See Table 15.3 for a list of maximum packet sizes for each FIFO configuration.
Table 15.3. FIFO Configurations
Endpoint
Number
0
1
2
3
Split Mode
Enabled?
N/A
N
Y
N
Y
N
Y
Maximum IN Packet Size (Double Maximum OUT Packet Size (Double
Buffer Disabled/Enabled)
Buffer Disabled/Enabled)
64
128/64
64/32
64/32
256/128
128/64
128/64
512/256
256/128
256/128
15.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
USB Register Definition 15.6. FIFOn: USB0 Endpoint FIFO Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
FIFODATA
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
USB Address:
0x20 - 0x23
USB Addresses 0x20–0x23 provide access to the 4 pairs of endpoint FIFOs:
IN/OUT Endpoint FIFO
0
1
2
3
USB Address
0x20
0x21
0x22
0x23
Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint.
Reading from the FIFO address unloads data from the OUT FIFO for the corresponding
endpoint.
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