C8051F321-GMR Datasheet, PDF (144/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
SFR Definition 15.3. USB0DAT: USB0 Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
USB0DAT
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x97
This SFR is used to indirectly read and write USB0 registers.
Write Procedure:
1. Poll for BUSY (USB0ADR.7) => ‘0’.
2. Load the target USB0 register address into the USBADDR bits in register USB0ADR.
3. Write data to USB0DAT.
4. Repeat (Step 2 may be skipped when writing to the same USB0 register).
Read Procedure:
1. Poll for BUSY (USB0ADR.7) => ‘0’.
2. Load the target USB0 register address into the USBADDR bits in register USB0ADR.
3. Write ‘1’ to the BUSY bit in register USB0ADR (steps 2 and 3 can be performed in the
same write).
4. Poll for BUSY (USB0ADR.7) => ‘0’.
5. Read data from USB0DAT.
6. Repeat from Step 2 (Step 2 may be skipped when reading the same USB0 register; Step 3
may be skipped when the AUTORD bit (USB0ADR.6) is logic 1).
USB Register
Name
IN1INT
OUT1INT
CMINT
IN1IE
OUT1IE
CMIE
FADDR
POWER
FRAMEL
FRAMEH
INDEX
CLKREC
FIFOn
Table 15.2. USB0 Controller Registers
USB Register
Address
0x02
0x04
0x06
0x07
0x09
0x0B
0x00
0x01
0x0C
0x0D
0x0E
0x0F
0x20-0x23
Description
Page Number
Interrupt Registers
Endpoint0 and Endpoints1-3 IN Interrupt Flags
153
Endpoints1-3 OUT Interrupt Flags
154
Common USB Interrupt Flags
155
Endpoint0 and Endpoints1-3 IN Interrupt Enables
156
Endpoints1-3 OUT Interrupt Enables
156
Common USB Interrupt Enables
157
Common Registers
Function Address
149
Power Management
151
Frame Number Low Byte
152
Frame Number High Byte
152
Endpoint Index Selection
145
Clock Recovery Control
146
Endpoints0-3 FIFOs
148
144
Rev. 1.4