C8051F321-GMR Datasheet, PDF (231/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
x0
000x
PCA Interrupt
PCA0CN
CC CCCCC
FR CCCCC
FFFFF
43210
Port I/O
Crossbar ^CEXn
0
1
0
1
PCA0CPLn
Capture
PCA
Timebase
PCA0L
Figure 20.4. PCA Capture Mode Diagram
PCA0CPHn
PCA0H
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
Rev. 1.4
231