C8051F321-GMR Datasheet, PDF (38/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
Figure 4.6. QFN-28 Recommended PCB Land Pattern
Table 4.5. QFN-28 PCB Land Pattern Dimesions
Dimension
Min
Max
Dimension
Min
C1
4.80
C2
4.80
E
0.50
X2
3.20
Y1
0.85
Y2
3.20
X1
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Max
3.30
0.95
3.30
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60m minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 3x3 array of 0.90mm openings on a 1.1mm pitch should be used for the center pad to
assure the proper paste volume (67% Paste Coverage).
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
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Rev. 1.4