C8051F321-GMR Datasheet, PDF (141/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
SFR Definition 15.1. USB0XCN: USB0 Transceiver Control
R/W
R/W
R/W
R/W
R/W
R
R
PREN PHYEN SPEED PHYTST1 PHYTST0 DFREC
Dp
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R
Reset Value
Dn 00000000
Bit0 SFR Address:
0xD7
Bit7:
Bit6:
Bit5:
Bits4–3:
PREN: Internal Pull-up Resistor Enable
The location of the pull-up resistor (D+ or D–) is determined by the SPEED bit.
0: Internal pull-up resistor disabled (device effectively detached from the USB network).
1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB net-
work).
PHYEN: Physical Layer Enable
This bit enables/disables the USB0 physical layer transceiver.
0: Transceiver disabled (suspend).
1: Transceiver enabled (normal).
SPEED: USB0 Speed Select
This bit selects the USB0 speed.
0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor appears
on the D– line.
1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor appears on
the D+ line.
PHYTST1–0: Physical Layer Test
These bits can be used to test the USB0 transceiver.
PHYTST[1:0]
00b
01b
10b
11b
Mode
Mode 0: Normal (non-test mode)
Mode 1: Differential ‘1’ Forced
Mode 2: Differential ‘0’ Forced
Mode 3: Single-Ended ‘0’ Forced
D+ D–
XX
10
01
00
Bit2:
Bit1:
Bit0:
DFREC: Differential Receiver
The state of this bit indicates the current differential value present on the D+ and D– lines
when PHYEN = ‘1’.
0: Differential ‘0’ signaling on the bus.
1: Differential ‘1’ signaling on the bus.
Dp: D+ Signal Status
This bit indicates the current logic level of the D+ pin.
0: D+ signal currently at logic 0.
1: D+ signal currently at logic 1.
Dn: D- Signal Status
This bit indicates the current logic level of the D– pin.
0: D– signal currently at logic 0.
1: D– signal currently at logic 1.
Rev. 1.4
141