C8051F321-GMR Datasheet, PDF (210/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
“14.1. Priority Crossbar Decoder” on page 128 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see Figure 19.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register INT01CF (see Figure 8.13). Setting GATE0 to ‘1’ allows
the timer to be controlled by the external input signal /INT0 (see Section “9.3.5. Interrupt Register Descrip-
tions” on page 90), facilitating pulse width measurements.
TR0
GATE0
0
X
1
0
1
1
1
1
X = Don't Care
/INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register INT01CF (see
Figure 8.13).
Pre-scaled Clock
SYSCLK
T0
Crossbar
GATE0
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
TMOD
GCT TGCT T
A / 11A / 00
T T MM T T MM
E110E010
1
0
0
INT01CF
IIIIIIII
NNNNNNNN
11110000
PSSSPSSS
LLLLLLLL
210 210
0
1
1
TR0
TCLK
TL0
(5 bits)
TH0
(8 bits)
/INT0
IN0PL _XOR
Figure 19.1. T0 Mode 0 Block Diagram
TF1
TR1
TF0
Interrupt
TR0
IE1
IT1
IE0
IT0
210
Rev. 1.4