C8051F321-GMR Datasheet, PDF (39/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
5. 10-Bit ADC (ADC0)
The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as
AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with
integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and
window detector are all configurable under software control via the Special Function Registers shown in
Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to mea-
sure P1.0-P3.0, the Temperature Sensor output, or VDD with respect to P1.0-P3.0, VREF, or GND. The
ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to
logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
P1.0
P1.7
P2.0
P2.4-2.7
available on
C8051F320
Temp
Sensor
P2.7
P3.0
VDD
P1.0
P2.4-2.7
available on
C8051F320
P1.7
P2.0
P2.7
P3.0
VREF
GND
AMX0P
ADC0CN
19-to-1
AMUX
19-to-1
AMUX
AMX0N
VDD
000
Start
Conversion ⁰⁰¹
010
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
011
Timer 1 Overflow
100
CNVSTR Input
10-Bit
(+)
SAR
101
Timer 3 Overflow
(-)
ADC
ADC0CF
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
AD0WINT
Window
Compare
32 Logic
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.4
39