C8051F321-GMR Datasheet, PDF (135/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
SFR Definition 14.9. P1MDOUT: Port1 Output Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
0xA5
Bits7–0:
Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis-
ter P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
SFR Definition 14.10. P1SKIP: Port1 Skip Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xD5
Bits7–0:
P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
SFR Definition 14.11. P2: Port2 Register
R/W
P2.7
Bit7
R/W
P2.6
Bit6
R/W
P2.5
Bit5
R/W
P2.4
Bit4
R/W
P2.3
Bit3
R/W
P2.2
Bit2
R/W
R/W
Reset Value
P2.1
P2.0 11111111
Bit1
Bit0 SFR Address:
(bit addressable) 0xA0
Bits7–0:
P2.[7:0]
Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port
pin when configured as digital input.
0: P2.n pin is logic low.
1: P2.n pin is logic high.
Note: P2.7–P2.4 only available on C8051F320 devices. Writes to these Ports do not require
XBARE = ‘1’.
Rev. 1.4
135