C8051F321-GMR Datasheet, PDF (224/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
19.3.3. USB Start-of-Frame Capture
When T3SOF = ‘1’, Timer 3 operates in USB Start-of-Frame (SOF) capture mode. When T3SPLIT = ‘0’,
Timer 3 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents
of the Timer 3 registers (TMR3H:TMR3L) are latched into the Timer 3 Reload registers
(TMR3RLH:TMR3RLL). A Timer 3 interrupt is generated if enabled. This mode can be used to calibrate the
system clock or external oscillator against the known USB host SOF clock.
TMR3CN
TTTTTT T
FFF33R 3
3 3 3SS3 X
HL LOP C
EFL L
NI K
T
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
0
TR3
1
USB
Start-of-Frame
(SOF)
TCLK _{TMR3L TMR3H}
Capture _{TMR3RLL TMR3RLH}
To ADC
Enable
Interrupt
Figure 19.10. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’)
When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents
of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
TMR3CN
TTTTTT T
FFF33R 3
3 3 3SS3 X
HL LOP C
EFL L
NI K
T
SYSCLK / 12
0
External Clock / 8
1
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
Capture
TMR3RLH
0
TCLK
TR3
TMR3H
To ADC
1
Enable
SYSCLK
1
Capture
TMR3RLL
TCLK _TMR3L
USB
Start-of-Frame
(SOF)
0
Figure 19.11. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’)
Interrupt
224
Rev. 1.4