C8051F321-GMR Datasheet, PDF (219/250 Pages) Silicon Laboratories – Full Speed USB, 16 k ISP FLASH MCU Family

C8051F320/1
19.2.3. USB Start-of-Frame Capture
When T2SOF = ‘1’, Timer 2 operates in USB Start-of-Frame (SOF) capture mode. When T2SPLIT = ‘0’,
Timer 2 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents
of the Timer 2 registers (TMR2H:TMR2L) are latched into the Timer 2 Reload registers
(TMR2RLH:TMR2RLL). A Timer 2 interrupt is generated if enabled. This mode can be used to calibrate the
system clock or external oscillator against the known USB host SOF clock.
TMR2CN
TTTTTT T
FFF22R 2
2 2 2SS2 X
HL LOP C
EFL L
NI K
T
CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMMA A
HLHL 10
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
0
TR2
1
USB
Start-of-Frame
(SOF)
TL2
Overflow
To SMBus
TCLK _{TMR2L TMR2H}
Capture _{TMR2RLL TMR2RLH}
To ADC,
SMBus
Enable
Interrupt
Figure 19.6. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’)
When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents
of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.
TMR2CN
TTTTTT T
FFF22R 2
2 2 2SS2 X
HL LOP C
EFL L
NI K
T
SYSCLK / 12
0
External Clock / 8
1
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
0
TR2
1
TMR2RLH ^Capture
TCLK
TMR2H
To SMBus
Enable
SYSCLK
1
0
Capture
TMR2RLL
TCLK _TMR2L
To ADC,
SMBus
USB
Start-of-Frame
(SOF)
Figure 19.7. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’)
Interrupt
Rev. 1.4
219