C8051F388-B Datasheet, PDF (81/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
11.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sec-
tions of the datasheet associated with their corresponding system function.
SFR Definition 11.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
3
2
1
0
Name
DPL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x82; SFR Page = All Pages
Bit Name
Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
SFR Definition 11.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
3
2
1
0
Name
DPH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x83; SFR Page = All Pages
Bit Name
Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
Rev. 1.1
81