C8051F388-B Datasheet, PDF (207/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 23.2. SMOD1: UART1 Mode
Bit
7
6
5
4
3
2
1
0
Name ^MCE1
S1PT[1:0]
PE1
S1DL[1:0]
XBE1
SBL1
Type ^R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
1
1
0
0
SFR Address = 0xE5; SFR Page = All Pages
Bit Name
Function
7 MCE1 _{Multiprocessor Communication Enable.}
0: RI will be activated if stop bit(s) are 1.
1: RI will be activated if stop bit(s) and extra bit are 1 (extra bit must be enabled using
XBE1).
Note: This function is not available when hardware parity is enabled.
6:5 S1PT[1:0] _{Parity Type Bits.}
00: Odd
01: Even
10: Mark
11: Space
4
PE1 _{Parity Enable.}
This bit activates hardware parity generation and checking. The parity type is selected
by bits S1PT1-0 when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
3:2 S1DL[1:0] _{Data Length.}
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
1 XBE1 _{Extra Bit Enable.}
When enabled, the value of TBX1 will be appended to the data field.
0: Extra Bit Disabled.
1: Extra Bit Enabled.
0 SBL1 _{Stop Bit Length.}
0: Short—Stop bit is active for one bit time.
1: Long—Stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
Rev. 1.1
207