C8051F388-B Datasheet, PDF (21/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the C8051F388/9/A/B
Name
Pin Numbers Type
Description
48-pin 32-pin
V_DD
10
6 Power In 2.7–3.6 V Power Supply Voltage Input.
GND
RST/
Power 3.3 V Voltage Regulator Output.
Out
7
3
Ground.
13
9
D I/O Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 μs.
C2CK
C2D
P3.0 /
D I/O ^{Clock signal for the C2 Debug Interface.}
14 — D I/O Bi-directional data signal for the C2 Debug Interface.
— 10 D I/O Port 3.0. See Section 20 for a complete description of Port 3.
C2D
REGIN
INT2
NC
NC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
D I/O Bi-directional data signal for the C2 Debug Interface.
11
7 Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
age regulator.
12
8
D In INT2 interrupt input.
8
4
This pin is a no-connect and can be left floating.
9
5
This pin is a no-connect and can be left floating.
6
2 D I/O or Port 0.0. See Section 20 for a complete description of Port 0.
A In
5
1 D I/O or Port 0.1.
A In
4
32 D I/O or Port 0.2.
A In
3
31 D I/O or Port 0.3.
A In
2
30 D I/O or Port 0.4.
A In
1
29 D I/O or Port 0.5.
A In
48 28 D I/O or Port 0.6.
A In
47 27 D I/O or Port 0.7.
A In
Rev. 1.1
21