C8051F388-B Datasheet, PDF (154/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
5
4
3
2
1
0
Name WEAKPUD XBARE
T1E
T0E
ECIE
PCA0ME[2:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE2; SFR Page = All Pages
Bit
Name
Function
7 WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6
XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5
T1E
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
4
T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
3
ECIE PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
2:0 PCA0ME[2:0] PCA Module I/O Enable Bits.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
11x: Reserved.
154
Rev. 1.1