C8051F388-B Datasheet, PDF (271/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
Table 26.3. Watchdog Timer Timeout Intervals¹
System Clock (Hz)
PCA0CPL4
Timeout Interval (ms)
48,000,000
255
16.4
48,000,000
128
8.3
48,000,000
32
2.1
12,000,000
255
65.5
12,000,000
128
33.0
12,000,000
32
1,500,000²
255
1,500,000²
128
1,500,000²
32
8.4
524.3
264.2
67.6
32,768
255
24,000
32,768
128
12,094
32,768
32
3,094
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Rev. 1.1
271