C8051F388-B Datasheet, PDF (147/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
20. Port Input/Output
Digital and analog resources are available through 40 I/O pins (C8051F388/A) or 25 I/O pins (C8051F389/
B). Port pins are organized as shown in Figure 20.1. Each of the Port pins can be defined as general-pur-
pose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital
resources as shown in Figure 20.3. The designer has complete control over which functions are assigned,
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 20.1, SFR
Definition 20.2, and SFR Definition 20.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4).
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
Rev. 1.1
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