C8051F388-B Datasheet, PDF (105/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
15. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F388/9/A/B's resources and periph-
erals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F388/9/A/B. This allows the addition of new functionality while retaining compatibility with the MCS-
51™ instruction set. Table 15.1 lists the SFRs implemented in the C8051F388/9/A/B device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 15.2, for a detailed description of each register.
15.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F388/9/A/B devices utilize two SFR pages: 0x0, and 0xF.
Most SFRs are available on both pages. SFR pages are selected using the Special Function Register
Page Selection register, SFRPAGE. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
Important Note: When reading or writing SFRs that are not available on all pages within an ISR, it is rec-
ommended to save the state of the SFRPAGE register on ISR entry, and restore state on exit.
SFR Definition 15.1. SFRPAGE: SFR Page
Bit
7
6
5
4
3
2
1
0
Name
SFRPAGE[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xBF; SFR Page = All Pages
Bit
Name
Function
7:0 SFRPAGE[7:0] SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
Rev. 1.1
105