C8051F388-B Datasheet, PDF (61/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
Figure 8.2. Comparator1 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “20.1. Priority Crossbar Decoder” on
page 148 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V_DD) + 0.25 V without damage or upset. The complete Comparator elec-
trical specifications are given in Section “5. Electrical Characteristics” on page 34.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 8.2 and SFR Definition 8.4). Selecting a longer response time reduces the Comparator supply current.
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