C8051F388-B Datasheet, PDF (199/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 22.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
Name
SBUF0[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x99; SFR Page = All Pages
Bit Name
Function
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Table 22.1. Timer Settings for Standard Baud Rates Using Internal Oscillator
Target
Baud
Actual
Baud
Rate (bps) Rate (bps)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
2400
230769
115385
57692
28846
14423
9615
2404
1202
230769
115385
57692
28846
14423
9615
2404
1202
230769
115385
57692
28846
14388
9615
2404
Baud
Rate
Error
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.08%
0.16%
0.16%
Oscillator
Divide
Factor
52
104
208
416
832
1248
4992
9984
104
208
416
832
1664
2496
9984
19968
208
416
832
1664
3336
4992
19968
Timer Clock
Source
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 48
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
SYSCLK
SYSCLK
SYSCLK / 4
SYSCLK / 4
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
SCA1-SCA0
(pre-scale
select*
XX
XX
XX
XX
01
01
00
10
XX
XX
XX
01
01
00
10
10
XX
XX
01
01
00
00
10
T1M
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
Timer 1
Reload
Value (hex)
0xE6
0xCC
0x98
0x30
0x98
0x64
0x30
0x98
0xCC
0x98
0x30
0x98
0x30
0x98
0x98
0x30
0x98
0x30
0x98
0x30
0x75
0x30
0x30
Rev. 1.1
199