C8051F388-B Datasheet, PDF (180/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 21.7. SMB0ADM: SMBus0 Slave Address Mask
Bit
7
6
5
4
3
2
1
0
Name
SLVM0[6:0]
EHACK0
Type
R/W
R/W
Reset
1
1
1
1
1
1
1
0
SFR Address = 0xCE; SFR Page = 0
Bit
Name
Function
7:1 SLVM0[6:0] SMBus0 Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM0[6:0] enables compari-
sons with the corresponding bit in SLV0[6:0]. Bits set to 0 are ignored (can be
either 0 or 1 in the incoming address).
0
EHACK0 Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
SFR Definition 21.8. SMB1ADR: SMBus1 Slave Address
Bit
7
6
5
4
3
2
1
0
Name
SLV1[6:0]
GC1
Type
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCF; SFR Page = F
Bit
Name
Function
7:1 SLV1[6:0] SMBus1 Hardware Slave Address.
Defines the SMBus1 Slave Address(es) for automatic hardware acknowledgment.
Only address bits which have a 1 in the corresponding bit position in SLVM1[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC1
General Call Address Enable.
When hardware address recognition is enabled (EHACK1 = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
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Rev. 1.1