C8051F388-B Datasheet, PDF (171/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Table 21.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time
Minimum SDA Hold Time
T_low – 4 system clocks
0
or
1 system clock + s/w delay^*
1
11 system clocks
3 system clocks
12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgment, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBnTOE bit set, Timer 3 (SMBus0) and Timer 5 (SMBus1) should be configured to overflow
after 25 ms in order to detect SCL low timeouts (see Section “21.3.4. SCL Low Timeout” on page 168).
The SMBus interface will force the associated timer to reload while SCL is high, and allow the timer to
count when SCL is low. The timer interrupt service routine should be used to reset SMBus communication
by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBnFTE bit. When this bit is set, the bus
will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 21.4).
21.4.2. SMBus Timing Control Register
The SMBus Timing Control Register (SMBTC) is used to restrict the detection of a START condition under
certain circumstances. In some systems where there is significant mis-match between the impedance or
the capacitance on the SDA and SCL lines, it may be possible for SCL to fall after SDA during an address
or data transfer. Such an event can cause a false START detection on the bus. These kind of events are
not expected in a standard SMBus or I2C-compliant system. In most systems this parameter should
not be adjusted, and it is recommended that it be left at its default value.
By default, if the SCL falling edge is detected after the falling edge of SDA (i.e. one SYSCLK cycle or
more), the device will detect this as a START condition. The SMBTC register is used to increase the
amount of hold time that is required between SDA and SCL falling before a START is recognized. An addi-
tional 2, 4, or 8 SYSCLKs can be added to prevent false START detection in systems where the bus condi-
tions warrant this.
Rev. 1.1
171