C8051F388-B Datasheet, PDF (42/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
6. 10-Bit ADC
ADC0 on the C8051F388/9/A/B is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold, and a programmable window detector. The ADC is fully configurable under soft-
ware control via Special Function Registers. The ADC may be configured to measure various different sig-
nals using the analog multiplexer described in Section “6.5. ADC0 Analog Multiplexer” on page 55. The
voltage reference for the ADC is selected as described in Section “7. Voltage Reference Options” on
page 58. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Figure 6.1. ADC0 Functional Block Diagram
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Rev. 1.1