C8051F388-B Datasheet, PDF (166/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
21. SMBus0 and SMBus1 (I²C Compatible)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I²C serial bus. The C8051F388/9/A/B
devices contain two SMBus interfaces, SMBus0 and SMBus1.
Reads and writes to the SMBus by the system controller are byte oriented with the SMBus interface auton-
omously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system
clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the
system clock used). A method of extending the clock-low duration is available to accommodate devices
with different speed capabilities on the same bus.
The SMBus may operate as a master and/or slave, and may function on a bus with multiple masters. The
SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration
logic, and START/STOP control and generation. The SMBus peripherals can be fully driven by software
(i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address recogni-
tion and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the
SMBus0 peripheral and the associated SFRs is shown in Figure 21.1. SMBus1 is identical, with the excep-
tion of the available timer options for the clock source, and the timer used to implement the SCL low time-
out feature. Refer to the specific SFR definitions for more details.
Figure 21.1. SMBus Block Diagram
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