C8051F388-B Datasheet, PDF (244/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
Figure 25.10. Timer 3 Capture Mode (T3SPLIT = 0)
When T3SPLIT = 1, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
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