C8051F388-B Datasheet, PDF (156/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 20.4. P0: Port 0
Bit
7
6
5
4
3
2
1
0
Name
P0[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x80; SFR Page = All Pages; Bit Addressable
Bit Name
Description
Write
7:0 P0[7:0] Port 0 Data.
0: Set output latch to logic
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
LOW.
1: Set output latch to logic
HIGH.
figured for digital I/O.
Read
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 20.5. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF1; SFR Page = All Pages
Bit
Name
Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
156
Rev. 1.1