C8051F388-B Datasheet, PDF (255/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
25.5.2. 8-bit Timers with Auto-Reload
When T5SPLIT is 1 and T5CE = 0, Timer 5 operates as two 8-bit timers (TMR5H and TMR5L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 25.15. TMR5RLL holds the reload value for
TMR5L; TMR5RLH holds the reload value for TMR5H. The TR5 bit in TMR5CN handles the run control for
TMR5H. TMR5L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 5 Clock Select bits (T5MH and T5ML in CKCON1) select either SYSCLK or
the clock defined by the Timer 5 External Clock Select bit (T5XCLK in TMR5CN), as follows:
T5MH
0
0
1
T5XCLK
0
1
X
TMR5H Clock Source
SYSCLK/12
External Clock/8
SYSCLK
T5ML
0
0
1
T5XCLK
0
1
X
TMR5L Clock Source
SYSCLK/12
External Clock/8
SYSCLK
The TF5H bit is set when TMR5H overflows from 0xFF to 0x00; the TF5L bit is set when TMR5L overflows
from 0xFF to 0x00. When Timer 5 interrupts are enabled, an interrupt is generated each time TMR5H over-
flows. If Timer 5 interrupts are enabled and TF5LEN (TMR5CN.5) is set, an interrupt is generated each
time either TMR5L or TMR5H overflows. When TF5LEN is enabled, software must check the TF5H and
TF5L flags to determine the source of the Timer 5 interrupt. The TF5H and TF5L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 25.15. Timer 5 8-Bit Mode Block Diagram
Rev. 1.1
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