C8051F388-B Datasheet, PDF (172/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 21.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
1
0
Name ENSMB0 INH0
BUSY0 EXTHOLD0 SMB0TOE SMB0FTE SMB0CS[1:0]
Type R/W
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC1; SFR Page = 0
Bit
Name
Function
7 ENSMB0 SMBus0 Enable.
This bit enables the SMBus0 interface when set to 1. When enabled, the interface
constantly monitors the SDA0 and SCL0 pins.
6
INH0
SMBus0 Slave Inhibit.
When this bit is set to logic 1, the SMBus0 does not generate an interrupt when
slave events occur. This effectively removes the SMBus0 slave from the bus. Mas-
ter Mode interrupts are not affected.
5
BUSY0 SMBus0 Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4 EXTHOLD0 SMBus0 Setup and Hold Time Extension Enable.
This bit controls the SDA0 setup and hold times according to Table 21.2.
0: SDA0 Extended Setup and Hold Times disabled.
1: SDA0 Extended Setup and Hold Times enabled.
3 SMB0TOE SMBus0 SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus0 forces
Timer 3 to reload while SCL0 is high and allows Timer 3 to count when SCL0 goes
low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in
reload while SCL0 is high. Timer 3 should be programmed to generate interrupts at
25 ms, and the Timer 3 interrupt service routine should reset SMBus0 communica-
tion.
2 SMB0FTE SMBus0 Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL0 and SDA0
remain high for more than 10 SMBus clock source periods.
1:0 SMB0CS[1:0] SMBus0 Clock Source Selection.
These two bits select the SMBus0 clock source, which is used to generate the
SMBus0 bit rate. The selected device should be configured according to
Equation 21.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
172
Rev. 1.1