C8051F388-B Datasheet, PDF (158/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 20.8. P1: Port 1
Bit
7
6
5
4
3
2
1
0
Name
P1[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x90; SFR Page = All Pages; Bit Addressable
Bit Name
Description
Write
7:0 P1[7:0] Port 1 Data.
0: Set output latch to logic
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
LOW.
1: Set output latch to logic
HIGH.
figured for digital I/O.
Read
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
SFR Definition 20.9. P1MDIN: Port 1 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P1MDIN[7:0]
Type
R/W
Reset
1*
1
1
1
1
1
1
1
SFR Address = 0xF2; SFR Page = All Pages
Bit
Name
Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
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Rev. 1.1