C8051F388-B Datasheet, PDF (174/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 21.3. SMBTC: SMBus Timing Control
Bit
7
6
5
4
3
2
1
0
Name
SMB1SDD[1:0]
SMB0SDD[1:0]
Type
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xB9; SFR Page = F
Bit
Name
Function
7:4
Unused Read = 0000b; Write = don’t care.
3:2 SMB1SDD[1:0] SMBus1 Start Detection Window
These bits increase the hold time requirement between SDA falling and SCL fall-
ing for START detection.
00: No additional hold time requirement (0-1 SYSCLK).
01: Increase hold time window to 2-3 SYSCLKs.
10: Increase hold time window to 4-5 SYSCLKs.
11: Increase hold time window to 8-9 SYSCLKs.
1:0 SMB0SDD[1:0] SMBus0 Start Detection Window
These bits increase the hold time requirement between SDA falling and SCL fall-
ing for START detection.
00: No additional hold time window (0-1 SYSCLK).
01: Increase hold time window to 2-3 SYSCLKs.
10: Increase hold time window to 4-5 SYSCLKs.
11: Increase hold time window to 8-9 SYSCLKs.
174
Rev. 1.1