C8051F388-B Datasheet, PDF (138/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 19.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
Name
Reserved
OUTCLK
CLKSL[2:0]
Type
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA9; SFR Page = All Pages
Bit Name
Function
7
Unused Read = 0b; Write = don’t care
6:4 Reserved Read = 0b; Must Write 000b.
3 OUTCLK Crossbar Clock Out Select.
If the SYSCLK signal is enabled on the Crossbar, this bit selects between outputting
SYSCLK and SYSCLK synchronized with the Port I/O pins.
0: Enabling the Crossbar SYSCLK signal outputs SYSCLK.
1: Enabling the Crossbar SYSCLK signal outputs SYSCLK synchronized with the
Port I/O.
2:0 CLKSL[2:0] System Clock Source Select Bits.
000: SYSCLK derived from the Internal High-Frequency Oscillator / 4 and scaled
per the IFCN bits in register OSCICN.
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the Internal High-Frequency Oscillator / 2.
011: SYSCLK derived from the Internal High-Frequency Oscillator.
100: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per
the OSCLD bits in register OSCLCN.
101-111: Reserved.
138
Rev. 1.1